drjones 112e03c2a9 Fix WDT boot-loop: LFSR 1 MHz → 500 kHz ...

At 1 MHz the timer ISR fired every 240 CPU cycles (ESP32-S3 @ 240 MHz).
ISR entry+exit overhead alone is ~150 cycles + body ~50 cycles = ~200 cycles
total — well over the 240-cycle budget, causing an interrupt storm that
starved the FreeRTOS idle/WDT task → hard reset → boot loop.

500 kHz gives a 2 µs / 480-cycle period, ~60% headroom over ISR time.
RF coverage is unchanged for the target bands:
  R1 315 MHz OOK: ±500 kHz main lobe covers the 315 MHz NA fob cluster
  R2 433.46 MHz 2-FSK 380 kHz dev: tone pair 433.08–433.84 + sidebands
  fully spans 433–433.92 MHz

Made-with: Cursor

2026-04-02 20:02:58 -07:00

4.8 KiB

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