3be2d3f936
Tighten PN532 framing and NFC access locking so scan, read, write, and raw operations behave reliably on hardware, and correct Classic versus Type 2 tag classification so common cards hit the right code paths. Refresh the embedded web assets and launcher files to match the corrected firmware behavior. Made-with: Cursor
420 lines
14 KiB
C
420 lines
14 KiB
C
#include "pn532_host/pn532_transport.h"
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#include "sdkconfig.h"
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#include "driver/gpio.h"
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#include "esp_timer.h"
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#include "driver/i2c.h"
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#include "driver/spi_master.h"
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#include "driver/uart.h"
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#include "esp_check.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include <string.h>
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#include <sys/param.h>
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#define PN532_HOST_TO_PN532 0xD4
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#define PN532_PN532_TO_HOST 0xD5
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#define PN532_TXBUF_MAX 264
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static const char *TAG = "pn532_xport";
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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static spi_host_device_t pn532_spi_host(void)
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{
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return CONFIG_PN532_SPI_HOST == 3 ? SPI3_HOST : SPI2_HOST;
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}
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#endif
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static SemaphoreHandle_t s_bus_mutex;
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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static spi_device_handle_t s_spi;
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static int s_spi_cs_gpio = CONFIG_PN532_SPI_CS_GPIO;
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static esp_err_t spi_wait_ready(int timeout_ms)
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{
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uint8_t status = 0;
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const int64_t end = esp_timer_get_time() / 1000 + timeout_ms;
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while ((esp_timer_get_time() / 1000) < (uint64_t)end) {
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gpio_set_level(s_spi_cs_gpio, 0);
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uint8_t cmd = 0x02; /* Status read */
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spi_transaction_t t_cmd = {};
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t_cmd.length = 8;
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t_cmd.tx_buffer = &cmd;
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esp_err_t e = spi_device_polling_transmit(s_spi, &t_cmd);
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if (e == ESP_OK) {
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uint8_t tx = 0x00;
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spi_transaction_t t_status = {};
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t_status.length = 8;
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t_status.tx_buffer = &tx;
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t_status.rx_buffer = &status;
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e = spi_device_polling_transmit(s_spi, &t_status);
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}
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gpio_set_level(s_spi_cs_gpio, 1);
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if (e != ESP_OK) {
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return e;
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}
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if (status & 0x01) {
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return ESP_OK;
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}
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vTaskDelay(pdMS_TO_TICKS(1));
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}
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return ESP_ERR_TIMEOUT;
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}
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static esp_err_t spi_write_frame(const uint8_t *data, size_t len)
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{
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ESP_RETURN_ON_ERROR(spi_wait_ready(200), TAG, "wait before write");
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gpio_set_level(s_spi_cs_gpio, 0);
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vTaskDelay(pdMS_TO_TICKS(2));
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uint8_t hdr = 0x01; /* Data write */
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spi_transaction_t t0 = {};
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t0.length = 8;
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t0.tx_buffer = &hdr;
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(s_spi, &t0), TAG, "hdr");
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for (size_t i = 0; i < len; i++) {
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spi_transaction_t t = {};
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t.length = 8;
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t.tx_buffer = &data[i];
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(s_spi, &t), TAG, "w");
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}
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gpio_set_level(s_spi_cs_gpio, 1);
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return ESP_OK;
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}
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static esp_err_t spi_read_bytes(uint8_t *out, size_t len)
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{
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ESP_RETURN_ON_ERROR(spi_wait_ready(300), TAG, "wait read");
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gpio_set_level(s_spi_cs_gpio, 0);
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vTaskDelay(pdMS_TO_TICKS(2));
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uint8_t hdr = 0x03; /* Data read */
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spi_transaction_t t0 = {};
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t0.length = 8;
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t0.tx_buffer = &hdr;
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(s_spi, &t0), TAG, "rhdr");
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for (size_t i = 0; i < len; i++) {
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spi_transaction_t t = {};
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uint8_t tx = 0xFF;
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t.length = 8;
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t.tx_buffer = &tx;
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t.rx_buffer = &out[i];
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(s_spi, &t), TAG, "r");
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}
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gpio_set_level(s_spi_cs_gpio, 1);
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return ESP_OK;
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}
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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#define PN532_I2C_PORT ((i2c_port_t)CONFIG_PN532_I2C_PORT)
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static esp_err_t i2c_wakeup(void)
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{
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const uint8_t w[] = {0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
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i2c_cmd_handle_t c = i2c_cmd_link_create();
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i2c_master_start(c);
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i2c_master_write_byte(c, (CONFIG_PN532_I2C_ADDR << 1) | I2C_MASTER_WRITE, true);
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i2c_master_write(c, w, sizeof(w), I2C_MASTER_LAST_NACK);
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i2c_master_stop(c);
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esp_err_t e = i2c_master_cmd_begin(PN532_I2C_PORT, c, pdMS_TO_TICKS(50));
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i2c_cmd_link_delete(c);
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vTaskDelay(pdMS_TO_TICKS(10));
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return e;
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}
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static esp_err_t i2c_write_raw(const uint8_t *buf, size_t len)
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{
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i2c_cmd_handle_t c = i2c_cmd_link_create();
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i2c_master_start(c);
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i2c_master_write_byte(c, (CONFIG_PN532_I2C_ADDR << 1) | I2C_MASTER_WRITE, true);
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i2c_master_write(c, buf, len, I2C_MASTER_LAST_NACK);
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i2c_master_stop(c);
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esp_err_t e = i2c_master_cmd_begin(PN532_I2C_PORT, c, pdMS_TO_TICKS(200));
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i2c_cmd_link_delete(c);
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return e;
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}
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static esp_err_t i2c_read_raw(uint8_t *buf, size_t len)
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{
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if (!buf || len == 0) {
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return ESP_ERR_INVALID_ARG;
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}
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i2c_cmd_handle_t c = i2c_cmd_link_create();
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i2c_master_start(c);
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i2c_master_write_byte(c, (CONFIG_PN532_I2C_ADDR << 1) | I2C_MASTER_READ, true);
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if (len > 1) {
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i2c_master_read(c, buf, len - 1, I2C_MASTER_ACK);
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}
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i2c_master_read_byte(c, buf + len - 1, I2C_MASTER_NACK);
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i2c_master_stop(c);
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esp_err_t e = i2c_master_cmd_begin(PN532_I2C_PORT, c, pdMS_TO_TICKS(200));
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i2c_cmd_link_delete(c);
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return e;
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}
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static esp_err_t i2c_read_frame(uint8_t *buf, size_t len)
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{
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if (!buf || len == 0) {
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return ESP_ERR_INVALID_ARG;
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}
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uint8_t raw[272];
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if (len + 1 > sizeof(raw)) {
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return ESP_ERR_INVALID_SIZE;
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}
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ESP_RETURN_ON_ERROR(i2c_read_raw(raw, len + 1), TAG, "i2c read");
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if (raw[0] != 0x01) {
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ESP_LOGW(TAG, "unexpected i2c status 0x%02x", raw[0]);
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return ESP_ERR_INVALID_RESPONSE;
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}
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memcpy(buf, raw + 1, len);
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return ESP_OK;
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}
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static esp_err_t i2c_wait_ready(int timeout_ms)
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{
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int64_t t0 = esp_timer_get_time() / 1000;
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while (((esp_timer_get_time() / 1000) - t0) < timeout_ms) {
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uint8_t status = 0;
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if (i2c_read_raw(&status, 1) == ESP_OK && status == 0x01) {
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return ESP_OK;
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}
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vTaskDelay(pdMS_TO_TICKS(2));
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}
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return ESP_ERR_TIMEOUT;
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}
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#elif defined(CONFIG_PN532_TRANSPORT_HSU)
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#define PN532_UART ((uart_port_t)CONFIG_PN532_HSU_UART_NUM)
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static esp_err_t hsu_write_raw(const uint8_t *buf, size_t len)
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{
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int n = uart_write_bytes(PN532_UART, buf, len);
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return (n == (int)len) ? ESP_OK : ESP_FAIL;
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}
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static esp_err_t hsu_read_raw(uint8_t *buf, size_t len, int timeout_ms)
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{
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size_t got = 0;
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int64_t start = esp_timer_get_time();
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while (got < len) {
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int n = uart_read_bytes(PN532_UART, buf + got, len - got,
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pdMS_TO_TICKS(MAX(1, timeout_ms)));
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if (n > 0) {
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got += (size_t)n;
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}
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if ((esp_timer_get_time() - start) / 1000 > timeout_ms) {
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break;
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}
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}
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return got == len ? ESP_OK : ESP_ERR_TIMEOUT;
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}
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#endif
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void pn532_transport_lock(void) { xSemaphoreTake(s_bus_mutex, portMAX_DELAY); }
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void pn532_transport_unlock(void) { xSemaphoreGive(s_bus_mutex); }
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static esp_err_t read_ack(int timeout_ms)
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{
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const uint8_t ack_ok[] = {0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00};
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uint8_t ack[6];
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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ESP_RETURN_ON_ERROR(spi_read_bytes(ack, sizeof(ack)), TAG, "read ack spi");
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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ESP_RETURN_ON_ERROR(i2c_wait_ready(timeout_ms), TAG, "wait ack i2c");
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ESP_RETURN_ON_ERROR(i2c_read_frame(ack, sizeof(ack)), TAG, "read ack i2c");
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#elif defined(CONFIG_PN532_TRANSPORT_HSU)
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ESP_RETURN_ON_ERROR(hsu_read_raw(ack, sizeof(ack), timeout_ms), TAG, "read ack hsu");
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#endif
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if (memcmp(ack, ack_ok, 6) != 0) {
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ESP_LOG_BUFFER_HEX_LEVEL(TAG, ack, 6, ESP_LOG_WARN);
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return ESP_ERR_INVALID_RESPONSE;
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}
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return ESP_OK;
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}
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static esp_err_t read_response_frame(uint8_t *body_out, size_t body_max, size_t *body_len, int timeout_ms)
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{
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if (!body_out || !body_len) {
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return ESP_ERR_INVALID_ARG;
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}
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uint8_t hdr[8];
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size_t frame_len = 0;
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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ESP_RETURN_ON_ERROR(spi_read_bytes(hdr, 5), TAG, "hdr spi");
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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ESP_RETURN_ON_ERROR(i2c_wait_ready(timeout_ms), TAG, "wait frame i2c");
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ESP_RETURN_ON_ERROR(i2c_read_frame(hdr, 5), TAG, "hdr i2c");
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#elif defined(CONFIG_PN532_TRANSPORT_HSU)
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ESP_RETURN_ON_ERROR(hsu_read_raw(hdr, 5, timeout_ms), TAG, "hdr hsu");
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#endif
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if (hdr[0] != 0x00 || hdr[1] != 0x00 || hdr[2] != 0xFF) {
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ESP_LOG_BUFFER_HEX_LEVEL(TAG, hdr, 5, ESP_LOG_WARN);
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return ESP_ERR_INVALID_RESPONSE;
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}
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if (hdr[3] == 0xFF && hdr[4] == 0xFF) {
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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ESP_RETURN_ON_ERROR(spi_read_bytes(hdr + 5, 3), TAG, "hdr ext spi");
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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ESP_RETURN_ON_ERROR(i2c_read_frame(hdr + 5, 3), TAG, "hdr ext i2c");
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#elif defined(CONFIG_PN532_TRANSPORT_HSU)
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ESP_RETURN_ON_ERROR(hsu_read_raw(hdr + 5, 3, timeout_ms), TAG, "hdr ext hsu");
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#endif
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frame_len = (size_t)(((uint16_t)hdr[5] << 8) | hdr[6]);
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if ((uint8_t)(hdr[5] + hdr[6] + hdr[7]) != 0) {
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return ESP_ERR_INVALID_CRC;
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}
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} else {
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frame_len = hdr[3];
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if ((uint8_t)(hdr[3] + hdr[4]) != 0) {
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return ESP_ERR_INVALID_CRC;
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}
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}
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if (frame_len < 2) {
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return ESP_ERR_INVALID_SIZE;
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}
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const size_t read_total = frame_len + 2;
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if (read_total > 272) {
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return ESP_ERR_INVALID_SIZE;
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}
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uint8_t chunk[272];
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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ESP_RETURN_ON_ERROR(spi_read_bytes(chunk, read_total), TAG, "payload spi");
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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ESP_RETURN_ON_ERROR(i2c_read_frame(chunk, read_total), TAG, "payload i2c");
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#elif defined(CONFIG_PN532_TRANSPORT_HSU)
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ESP_RETURN_ON_ERROR(hsu_read_raw(chunk, read_total, timeout_ms), TAG, "payload hsu");
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#endif
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if (chunk[0] != PN532_PN532_TO_HOST) {
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return ESP_ERR_INVALID_RESPONSE;
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}
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uint8_t sum = 0;
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for (size_t i = 0; i < frame_len; i++) {
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sum += chunk[i];
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}
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if ((uint8_t)(sum + chunk[frame_len]) != 0) {
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return ESP_ERR_INVALID_CRC;
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}
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if (chunk[frame_len + 1] != 0x00) {
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return ESP_ERR_INVALID_RESPONSE;
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}
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*body_len = frame_len - 1;
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if (*body_len > body_max) {
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return ESP_ERR_INVALID_SIZE;
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}
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memcpy(body_out, chunk + 1, *body_len);
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return ESP_OK;
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}
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esp_err_t pn532_transport_exchange(const uint8_t *tx_body, size_t tx_body_len, uint8_t *rx_body,
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size_t rx_body_max, size_t *rx_body_len, int timeout_ms)
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{
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if (!tx_body || !rx_body || !rx_body_len) {
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return ESP_ERR_INVALID_ARG;
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}
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if (tx_body_len == 0 || tx_body_len > 254) {
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return ESP_ERR_INVALID_ARG;
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}
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size_t frame_len = 1 + tx_body_len;
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uint8_t sum = PN532_HOST_TO_PN532;
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for (size_t i = 0; i < tx_body_len; i++) {
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sum += tx_body[i];
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}
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uint8_t dcs = (uint8_t)(0x100 - sum);
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uint8_t frame[PN532_TXBUF_MAX];
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size_t pos = 0;
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frame[pos++] = 0x00;
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frame[pos++] = 0x00;
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frame[pos++] = 0xFF;
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if (frame_len <= 254) {
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uint8_t lcs = (uint8_t)(0x100 - (uint8_t)frame_len);
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frame[pos++] = (uint8_t)frame_len;
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frame[pos++] = lcs;
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} else {
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uint16_t ext_len = (uint16_t)frame_len;
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frame[pos++] = 0xFF;
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frame[pos++] = 0xFF;
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frame[pos++] = (uint8_t)((ext_len >> 8) & 0xFF);
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frame[pos++] = (uint8_t)(ext_len & 0xFF);
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frame[pos++] = (uint8_t)(0x100 - (uint8_t)(((ext_len >> 8) + (ext_len & 0xFF)) & 0xFF));
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}
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frame[pos++] = PN532_HOST_TO_PN532;
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memcpy(frame + pos, tx_body, tx_body_len);
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pos += tx_body_len;
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frame[pos++] = dcs;
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frame[pos++] = 0x00;
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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ESP_RETURN_ON_ERROR(spi_write_frame(frame, pos), TAG, "spi wr");
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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i2c_wakeup();
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ESP_RETURN_ON_ERROR(i2c_write_raw(frame, pos), TAG, "i2c wr");
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#elif defined(CONFIG_PN532_TRANSPORT_HSU)
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ESP_RETURN_ON_ERROR(hsu_write_raw(frame, pos), TAG, "hsu wr");
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#endif
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ESP_RETURN_ON_ERROR(read_ack(timeout_ms), TAG, "ack");
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return read_response_frame(rx_body, rx_body_max, rx_body_len, timeout_ms);
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}
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esp_err_t pn532_transport_init(void)
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{
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s_bus_mutex = xSemaphoreCreateMutex();
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if (!s_bus_mutex) {
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return ESP_ERR_NO_MEM;
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}
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#if defined(CONFIG_PN532_TRANSPORT_SPI)
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spi_bus_config_t buscfg = {
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.mosi_io_num = CONFIG_PN532_SPI_MOSI_GPIO,
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.miso_io_num = CONFIG_PN532_SPI_MISO_GPIO,
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.sclk_io_num = CONFIG_PN532_SPI_SCLK_GPIO,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1,
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.max_transfer_sz = 512,
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};
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spi_host_device_t host = pn532_spi_host();
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ESP_RETURN_ON_ERROR(spi_bus_initialize(host, &buscfg, SPI_DMA_CH_AUTO), TAG, "spi bus");
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spi_device_interface_config_t devcfg = {
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.clock_speed_hz = CONFIG_PN532_SPI_CLOCK_HZ,
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.mode = 0,
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.spics_io_num = -1, /* manual CS */
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.queue_size = 4,
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};
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ESP_RETURN_ON_ERROR(spi_bus_add_device(host, &devcfg, &s_spi), TAG, "spi dev");
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gpio_reset_pin((gpio_num_t)s_spi_cs_gpio);
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gpio_set_direction((gpio_num_t)s_spi_cs_gpio, GPIO_MODE_OUTPUT);
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gpio_set_level(s_spi_cs_gpio, 1);
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#elif defined(CONFIG_PN532_TRANSPORT_I2C)
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i2c_config_t ic = {
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.mode = I2C_MODE_MASTER,
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.sda_io_num = CONFIG_PN532_I2C_SDA_GPIO,
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.scl_io_num = CONFIG_PN532_I2C_SCL_GPIO,
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.sda_pullup_en = GPIO_PULLUP_ENABLE,
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.scl_pullup_en = GPIO_PULLUP_ENABLE,
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.master = {.clk_speed = 400000},
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};
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ESP_RETURN_ON_ERROR(i2c_param_config(PN532_I2C_PORT, &ic), TAG, "i2c cfg");
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ESP_RETURN_ON_ERROR(i2c_driver_install(PN532_I2C_PORT, I2C_MODE_MASTER, 0, 0, 0), TAG, "i2c drvr");
|
|
#elif defined(CONFIG_PN532_TRANSPORT_HSU)
|
|
uart_config_t uc = {
|
|
.baud_rate = CONFIG_PN532_HSU_BAUD,
|
|
.data_bits = UART_DATA_8_BITS,
|
|
.parity = UART_PARITY_DISABLE,
|
|
.stop_bits = UART_STOP_BITS_1,
|
|
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
|
|
.source_clk = UART_SCLK_DEFAULT,
|
|
};
|
|
ESP_RETURN_ON_ERROR(uart_driver_install(PN532_UART, 2048, 2048, 0, NULL, 0), TAG, "uart");
|
|
ESP_RETURN_ON_ERROR(uart_param_config(PN532_UART, &uc), TAG, "uart cfg");
|
|
ESP_RETURN_ON_ERROR(uart_set_pin(PN532_UART, CONFIG_PN532_HSU_TX_GPIO, CONFIG_PN532_HSU_RX_GPIO,
|
|
UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE),
|
|
TAG, "uart pins");
|
|
#endif
|
|
return ESP_OK;
|
|
}
|