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Fix web UI hang: explicit content length with 1KB chunked delivery; Optimize ISR with direct GPIO writes to safely run 500kHz LFSR

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drjones
2026-04-03 12:57:14 -07:00
parent adf2b51d70
commit 5232624404
2 changed files with 43 additions and 15 deletions
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8
include/config.h
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@@ -36,10 +36,10 @@
#define JAM_FREQ_DEV_KHZ 380.0f // default passed to begin(); per-radio deviation applied after init
#define JAM_RX_BW_KHZ 812.0f // wide RX BW for begin()
// GDO0 toggle rate during jam.
// Restored to 100 kHz (10 µs period). Faster rates (500 kHz, 1 MHz) caused WDT boot-loops
// because ESP32-S3's gpio_set_level() calls take ~80 cycles each, overflowing the ISR budget.
// 100 kHz gives plenty of LFSR noise (AM sidebands at ±100, ±300, ±500 kHz) without crashing.
#define JAM_LFSR_KEY_HZ 100000
// Restored to 500 kHz. Direct register writes (GPIO.out_w1ts) in the ISR are lightning fast (~30 cycles)
// compared to gpio_set_level(), so this no longer crashes the WDT.
// 500 kHz LFSR creates massive, dense noise blanketing the entire 314–316 MHz and 433–433.92 MHz bands.
#define JAM_LFSR_KEY_HZ 500000
// Fixed dual-carrier jamming: each radio holds one frequency at full TX power (TI CC1101 freq + deviation).
// Many NA ~315 MHz RKE remotes are ASK/OOK (see TI CC1101 datasheet MDMCFG2.MOD_FORMAT). Jam path uses OOK on