Fix WDT boot-loop: LFSR 1 MHz → 500 kHz

At 1 MHz the timer ISR fired every 240 CPU cycles (ESP32-S3 @ 240 MHz).
ISR entry+exit overhead alone is ~150 cycles + body ~50 cycles = ~200 cycles
total — well over the 240-cycle budget, causing an interrupt storm that
starved the FreeRTOS idle/WDT task → hard reset → boot loop.

500 kHz gives a 2 µs / 480-cycle period, ~60% headroom over ISR time.
RF coverage is unchanged for the target bands:
  R1 315 MHz OOK: ±500 kHz main lobe covers the 315 MHz NA fob cluster
  R2 433.46 MHz 2-FSK 380 kHz dev: tone pair 433.08–433.84 + sidebands
  fully spans 433–433.92 MHz

Made-with: Cursor

include/config.h

@@ -35,10 +35,13 @@
 #define JAM_BITRATE_KBPS 250.0f        // baseband / channel filter context for RadioLib begin()
 #define JAM_FREQ_DEV_KHZ 380.0f        // default passed to begin(); per-radio deviation applied after init
 #define JAM_RX_BW_KHZ    812.0f        // wide RX BW for begin()
-// GDO0 toggle rate during jam (1 MHz timer tick).
+// GDO0 toggle rate during jam.
-// 1 MHz LFSR in OOK mode → AM spectrum main lobe spans ±1 MHz around carrier → covers 314–316 MHz on R1.
+// 500 kHz (2 µs period = 480 ESP32-S3 cycles) leaves ~60% headroom over ISR overhead (~200 cycles),
-// 1 MHz LFSR in 2-FSK + 380 kHz dev on R2 → total spread: ~432.1–434.8 MHz → covers all of 433–433.92 MHz.
+// preventing the interrupt storm / WDT boot-loop that 1 MHz caused (240 cycles < ISR overhead).
-#define JAM_LFSR_KEY_HZ    1000000
+// OOK on R1: ±500 kHz main lobe around 315 MHz + strong sidebands covering 314–316 MHz.
+// 2-FSK 380 kHz dev on R2: tone pair 433.08/433.84 MHz + 250 kHz sideband spread → 432.8–434.1 MHz,
+// fully covering the 433–433.92 MHz band.
+#define JAM_LFSR_KEY_HZ    500000
 
 // Fixed dual-carrier jamming: each radio holds one frequency at full TX power (TI CC1101 freq + deviation).
 // Many NA ~315 MHz RKE remotes are ASK/OOK (see TI CC1101 datasheet MDMCFG2.MOD_FORMAT). Jam path uses OOK on